Bøger i Analog Circuits and Signal Processing serien

This book provides readers with a single-source guide to fabricate, characterize and model memristor devices for sensing applications.

This book discusses design techniques, layout details and measurements of several key analog building blocks that currently limit the performance of 5G and E-Band transceivers implemented in deep-scaled CMOS.

This book describes the PREMISS system, which enables readers to overcome the limitations of state-of-the-art battery-less wireless sensors in size, cost, robustness and range, with a system concept for a 60 GHz wireless sensor system with monolithic sensors.

This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;Offers design guidelines to reduce couplings by adding specific protections.

This book presents fundamental requirements, electrical specification, and parameter tradeoffs of wearable EEG acquisition circuits, especially those compatible with dry electrodes for user-friendly recordings.

It covers the complete design flow, from link budget assessment to the transistor-level design of different RF front-end blocks, such as mixers and power amplifiers, presenting different alternatives and discussing the existing trade-offs.

This book presents a tutorial review of van der Pol model, a universal oscillator model for the analysis of modern RC-oscillators in weak and strong nonlinear regimes. A detailed analysis of the injection locking in van der Pol oscillators is also presented. The relation between the van der Pol parameters and several circuit implementations in CMOS nanotechnology is given, showing that this theory is very useful in the optimization of oscillator key parameters, such as: frequency, amplitude and phase relationship. The authors discuss three different examples: active coupling RC-oscillators, capacitive coupling RC-oscillators, and two-integrator oscillator working in the sinusoidal regime.· Provides a detailed tutorial on the van der Pol oscillator model, which can be the basis for the analysis of modern RC-oscillators in weak and strong nonlinear regimes;· Demonstrations the relationship between the van der Pol parameters and several circuit implementations in CMOS nanotechnology, showing that this theory is a powerful tool in the optimization of key oscillator parameters;· Provides three circuit prototypes implemented in modern CMOS nanotechnology in the GHz range, with applications in low area, low power, low cost, wireless sensor network (WSN) applications (e.g. IoT, BLE).

This book discusses the design and implementation aspects of ultra-low power biosignal acquisition platforms that exploit analog-assisted and algorithmic approaches for power savings.The authors describe an approach referred to as "analog-and-algorithm-assisted" signal processing.This enables significant power consumption reductions by implementing low power biosignal acquisition systems, leveraging analog preprocessing and algorithmic approaches to reduce the data rate very early in the signal processing chain.They demonstrate savings for wearable sensor networks (WSN) and body area networks (BAN), in the sensors' stimulation power consumption, as well in the power consumption of the digital signal processing and the radio link. Two specific implementations, an adaptive sampling electrocardiogram (ECG) acquisition and a compressive sampling (CS) photoplethysmogram (PPG) acquisition system, are demonstrated.First book to present the so called, "analog-and-algorithm-assisted" approaches for ultra-low power biosignal acquisition and processing platforms;Covers the recent trend of "beyond Nyquist rate" signal acquisition and processing in detail, including adaptive sampling and compressive sampling paradigms;Includes chapters on compressed domain feature extraction, as well as acquisition of photoplethysmogram, an emerging optical sensing modality, including compressive sampling based PPG readout with embedded feature extraction;Discusses emerging trends in sensor fusion for improving the signal integrity, as well as lowering the power consumption of biosignal acquisition systems.

¿This book describes an ECG processing architecture that guides biomedical SoC developers, from theory to implementation and testing. The authors provide complete coverage of the digital circuit implementation of an ultra-low power biomedical SoC, comprised of a detailed description of an ECG processor implemented and fabricated on chip. Coverage also includes the challenges and tradeoffs of designing ECG processors.Describes digital circuit architecture for implementing ECG processing algorithms on chip;Includes coverage of signal processing techniques for ECG processing;Features ultra-low power circuit design techniques;Enables design of ECG processing architectures and their respective on-chip implementation.

This book explains concepts behind fractional subsampling-based frequency synthesis that is re-shaping today's art in the field of low-noise LO generation.

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods.In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurementsfrom the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.

¿This book describes an ECG processing architecture that guides biomedical SoC developers, from theory to implementation and testing. The authors provide complete coverage of the digital circuit implementation of an ultra-low power biomedical SoC, comprised of a detailed description of an ECG processor implemented and fabricated on chip. Coverage also includes the challenges and tradeoffs of designing ECG processors.Describes digital circuit architecture for implementing ECG processing algorithms on chip;Includes coverage of signal processing techniques for ECG processing;Features ultra-low power circuit design techniques;Enables design of ECG processing architectures and their respective on-chip implementation.

This book presents state-of-the-art techniques for radiation hardened high-resolution Time-to-Digital converters and low noise frequency synthesizers. Throughout the book, advanced degradation mechanisms and error sources are discussed and several ways to prevent such errors are presented. An overview of the prerequisite physics of nuclear interactions is given that has been compiled in an easy to understand chapter. The book is structured in a way that different hardening techniques and solutions are supported by theory and experimental data with their various tradeoffs.Based on leading-edge research, conducted in collaboration between KU Leuven and CERN, the European Center for Nuclear ResearchDescribes in detail advanced techniques to harden circuits against ionizing radiationProvides a practical way to learn and understand radiation effects in time-based circuitsIncludes an introduction to the underlying physics, circuit design, and advanced techniques accompanied with experimental data

This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;Offers design guidelines to reduce couplings by adding specific protections.

It covers the complete design flow, from link budget assessment to the transistor-level design of different RF front-end blocks, such as mixers and power amplifiers, presenting different alternatives and discussing the existing trade-offs.

With the popularity of hardware security research, several edited monograms have been published, which aim at summarizing the research in a particular field.

This book introduces the origin of biomedical signals and the operating principles behind them and introduces the characteristics of common biomedical signals for subsequent signal measurement and judgment.

Few people know what wandering spurs are; fewer still know how to get rid of them. This book, which is written by those who raised awareness of wandering spurs, explained how they arise, and invented ways to get rid of them, contains valuable insights, analytical techniques and examples that will enable the reader to become an expert in the area. The book is aimed at circuit design professionals who need to ensure that their designs are not compromised by wandering spurs. In addition to insights, theory, and analysis, it contains practical circuit solutions, the performance of which are characterized experimentally.This book explains¿using simulation, analysis, and experimental measurements¿what wandering spurs are, how they arise, how to characterize them and, most importantly, how to get rid of them. The authors present not only theoretical analysis and simulation strategies, but also provide an overview of spectral analysis techniques for studying the phenomenon and convincing experimental results from both commercially available and custom-designed monolithic synthesizers. Explains what wandering spurs are and how they differ qualitatively from the well-known fixed spurs that plague fractional-N frequency synthesizers;Provides analytical and simulation methods to study wandering spurs and original analysis of the cause of this recently reported spectral phenomenon;Presents and analyses theoretical designs based on a conventional MASH 1-1-1 to mitigate wandering spurs;Describes measured performance for the discussed designs, confirming their effectiveness in mitigating wandering spurs.

A comprehensive study of silicon-based distributed architectures in wideband circuits are presented in this book. Novel circuit architectures for ultra-wideband (UWB) wireless technologies are described. The book begins with an introduction of several transceiver architectures for UWB. The discussion then focuses on RF front-end of the UWB radio. Therefore, the book will be of interest to RF circuit designers and students.

"e;Design of high voltage xDSL line drivers in standard CMOS"e; fits in the quest for highly efficient fully integrated xDSL modems for central office applications. The book focusses on the line driver, the most demanding building block of the xDSL modem for lowering power. To reduce the cost, the cheapest technology is selected: standard CMOS, without any extra process options to increase the nominal supply voltage. The emphasis lies on the analysis, design and implementation of high voltage highly efficient line drivers in mainstream CMOS."e;Design of high voltage xDSL line drivers in standard CMOS"e; covers the total design flow of monolithic CMOS high voltage circuits. The book is essential reading for analog design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.

Biopotential Readout Circuits for Portable Acquisition Systems describes one of the main building blocks of such miniaturized biomedical signal acquisition systems. The focus of this book is on the implementation of low-power and high-performance integrated circuit building blocks that can be used to extract biopotential signals from conventional biopotential electrodes. New instrumentation amplifier architectures are introduced and their design is described in detail. These amplifiers are used to implement complete acquisition demonstrator systems that are a stepping stone towards practical miniaturized and low-power systems.

This book describes a variety of current feedback operational amplifier (CFOA) architectures and their applications in analog signal processing/generation. Coverage includes a comprehensive survey of commercially available, off-the-shelf integrated circuit CFOAs, as well as recent advances made on the design of CFOAs, including design innovations for bipolar and CMOS CFOAs. This book serves as a single-source reference to the topic, as well as a catalog of over 200 application circuits which would be useful not only for students, educators and researchers in apprising them about the recent developments in the area but would also serve as a comprehensive repertoire of useful circuits for practicing engineers who might be interested in choosing an appropriate CFOA-based topology for use in a given application.

Whether you are a researcher, or practising engineer, or even non-familiar with power amplifiers student, it is a good idea to look into Advanced Design Techniques for RF Power Amplifiers.Its main aim is to provide the reader with a deep analysis of theoretical aspects, modelling, and design strategies of RF high-efficiency power amplifiers. Advanced Design Techniques for RF Power Amplifiers begins with an analytical review of current state of the problem. Then it moves to the theoretical analysis of BJT class-F power amplifier near transition frequency and presents the necessary realization conditions. The next part concerns the practical verification and demonstration of the theoretical results. It is followed by the part devoted to the output networks of high-efficiency power ampifiers. The novel type of photonic band-gap structure providing improved characteristics both in the pass and stop bands is proposed. Finally, the fifth-harmonic peaking class F power amplifier design based on the above structure is presented. Advanced Design Techniques for RF Power Amplifiers can be used as a guide by scientists and engineers dealing with this subject and as a text book to graduate and postgraduate students. The latter will find the comprehensive nonlinear power amplifiers simulation tutorial in the Appendix. It provides an excellent quick start for beginners, although the main contents is intended for a skilled reader.

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input.2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.

This book describes the design of optical receivers that use the most economical integration technology, while enabling performance that is typically only found in very expensive devices. To achieve this, all necessary functionality, from light detection to digital output, is integrated on a single piece of silicon. All building blocks are thoroughly discussed, including photodiodes, transimpedance amplifiers, equalizers and post amplifiers.

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods.In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurementsfrom the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.