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Reviews the major design methodologies that have had a profound effect on designing future Network-on-Chip (NoC) architectures. More precisely, the book addresses the problem of NoC design in the deterministic context, where the application and the architecture are modelled as graphs with worst-case type of information.
Presenting a mathematical model for on-chip routers which can be used for NoC performance analysis, this book reflects the shift from computation- to communication-based design that has resulted from the increasing complexity of so-called 'systems-on-chip'.
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