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Advanced HDL Synthesis and SOC Prototyping - Vaibbhav Taraate - Bog

- RTL Design Using Verilog

af Vaibbhav Taraate
Advanced HDL Synthesis and SOC Prototyping af Vaibbhav Taraate
Bag om Advanced HDL Synthesis and SOC Prototyping

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs.

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  • Sprog:
  • Engelsk
  • ISBN:
  • 9789811087752
  • Indbinding:
  • Hardback
  • Sideantal:
  • 307
  • Udgivet:
  • 18. januar 2019
  • Udgave:
  • 12019
  • Vægt:
  • 664 g.
  • 8-11 hverdage.
  • 7. december 2024

Normalpris

  • BLACK NOVEMBER

Medlemspris

Prøv i 30 dage for 45 kr.
Herefter fra 79 kr./md. Ingen binding.

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Beskrivelse af Advanced HDL Synthesis and SOC Prototyping

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs.

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