Low Power VLSI Circuit Design - Dr Sanjay (Centre for the Study of Developing Societies India) Kumar - Bog

Over the last years,researchers are searching for new low power solutions for VLSI circuits.This work focuses on reducing power dissipation,which is showing ever increasing growth with scaling down of technologies.Various techniques at different levels of design process have been implemented to reduce the power dissipation at circuit, architectural & system level.Furthermore,number of gates/chip area is constantly increasing,while switching energy does not decrease at same rate,so power dissipation rises becomes more difficult and expensive.Then, to limit the power dissipation, alternative solutions at each level of abstraction are proposed.The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers.This work focuses on a new CMOS logic family called ADIABATIC LOGIC, based on the adiabatic switching principle.The adiabatic logic structure dramatically reduces the power dissipation.Adiabatic logic offers a way to reuse the energy stored in the load capacitors rather than the traditional way of discharging the load capacitors to the ground and wasting this energy.